Integrated circuits typically use one or more clock signals to synchronize components and functions of the integrated circuit. Clock “trees” are used to branch these clock signals through buffers from a common source to components located in various areas on the integrated circuit. For example, a given source clock signal may feed into three buffers to produce three clock signals at a second branch level, which may feed into three more buffers to produce nine clock signals at a third branch level. The clock signals at any level can be used for clocking associated synchronous components and thereby coordinating the functions within the integrated circuit. It is therefore important that the clock signals at any particular level have a predefined phase relationship to one another.
For various reasons, however, any two clock signals at the same level of the same clock tree may be slightly out of phase with one another or do not otherwise have the desired phase relationship. This phase difference between clock signals is called “clock skew.” Clock skew can have several causes. For example, the buffers between levels in the clock tree typically introduce a delay between their inputs and outputs, so clock signals at different levels in the clock tree are naturally skewed from each other. Additionally, the load experienced by one clock signal may introduce a delay into the clock signal net that is different from the delay along another clock signal net. Also, routing differences between clock signal nets can result in differences in different resistances between the routes and therefore different propagation delays along the routes. Furthermore, changes in temperature, different applied voltages and tolerances in semiconductor fabrication processes can affect clock skew.
Occasionally, the skew between two clock signals is introduced intentionally to precisely coordinate the operation of two components in the integrated circuits. In any case, the skew must be tightly controlled for the integrated circuit to operate at desired high operating clock frequencies, where all or a portion of the synchronous components of the integrated circuit must switch states simultaneously or synchronously.
Common integrated circuit fabrication techniques try to minimize clock tree skew by resizing buffers in the clock tree to advance or delay transitions of the clock signals or by adding redundant loads to the circuits to balance the loading of the clock tree. Both of these techniques alter the delay of some clock signals relative to other clock signals by specified amounts that are determined by analysis of the timing of the clock signals. However, temperature changes, differences in applied voltages, differences in silicon fabrication processes and inadequate tolerances in the silicon fabrication processes can cause the actual clock skew to vary significantly from the nominal value, even with the above techniques. Improved clock tree deskew methodologies are therefore desired to achieve higher performance out of existing and future integrated circuit technologies.